The challenges of GSCM implementation in the UK manufacturing SMEs

The importance of green supply chain management has long attracted the interest of both researchers and practitioners in the industry. As environmental concerns are becoming one of the major issues discussed in the 21st century, countries with manufacturing as its principal economy contributor are always on the lookout for innovations and new approaches to balance both environmental considerations and profit making. The UK, being one of the top manufacturing countries in the world already considered green initiatives among their manufacturers. According to reports from the industry, large and international manufacturing companies from the UK have successfully implemented some green initiatives with significant improvements across the supply chain. However, the adoption of green initiatives is mainly focused on large companies rather the real backbone of the UK manufacturing industry, which is the small and medium-sized enterprises (SMEs). This paper therefore sets out to determine the implementation level of green supply chain among the SMEs. The paper adopts a mixed methods based approach and findings are based on 57 survey responses and 5 semi-structured interviews from UK manufacturing SMEs. The findings show that the level of GSCM implementation among the UK manufacturing SMEs is low compared to large organisations. Cost of implementing GSCM practices emerged as a key challenge faced by the UK manufacturing SMEs which was followed by the lack of knowledge within the organisation. This study thus adds to the limited literature on the manufacturing SMEs and provides evidence from the UK manufacturing sector on the adoption of GSCM practices

Modeling analog signal routing for wideband mmW phased arrays

Abstract. Modern communication systems look for higher operating frequencies to find more bandwidth to enable higher data rates. At a same time, these systems use larger and larger antenna arrays to compensate for the increased propagation losses by using antenna directivity. Often these systems use phased array approach for realizing steerable beam patterns. In phased arrays, the signal is usually divided in analogue domain to multiple transmit paths and combined in analogue domain from multiple receive paths. In this thesis, the aim is to generate a wideband modelling approach for analog signal routing in phased array transceivers that use radio frequency (RF) beamforming. In particular, the aim is to model the transfer functions of different signal paths from the sum node of all paths to the individual antennas and finally to the free space, to form a three-dimensional beam pattern that has frequency selective beam squint. The modelling approach and their behaviour in different symmetric and asymmetric beamforming architectures are presented and the performance of the system is observed through simulations by using beam patterns and equivalent amplitude responses in different directions. The impacts of array size, steering angle, and relative bandwidth are studied for the observed beam squint with different signal routing architectures to find their bandwidth limitations in different scenarios. The routing model also includes the impact of the dielectric materials of the circuit implementations

Lean manufacturing adoption in the transport and logistics sector of Thailand - An exploratory study

This paper investigates the adoption status of lean manufacturing (LM) in the transport and logistics sector of Thailand. A survey questionnaire was design, validated and distributed among Thai transport and logistics companies. In total, 120 useable responses were received and analysed using descriptive statistics. The results of the study indicate that the implementation of LM is relatively high, with PDCA, 5S and root cause analysis being the most implemented LM approaches and tools. However, the LM’s implementation was found to be mainly contained within individual departments or improvement projects, rather than being a company’s wide strategy. Main challenges to LM implementation included: organisational structure of companies, misalignment between goals of individuals and their companies, and lack of sustainment of a lean culture. Main benefits were the ability to identify and reduce waste, increased productivity and better organisation of workstations. On the other hand, lack of understanding, knowledge and expertise in LM were the main reasons for not implementing it, plus the use of technology-based tools instead of LM. Non-LM companies showed interest in adopting LM in the future, with JIT, Kaizen and Six Sigma being the most likely to implement. This study is among the very first of its kind. It offers academics, researchers and practitioners interested in LM and/or the transport and logistics sector with some initial evidence of the adoption of LM in this industrial sector of Thailand

Growth, debt, and sovereign risk in a small, open economy

The continuing debt crisis that many developing countries have faced in the current decade has underscored the need to understand the relationships between debt accumulation and growth, as well as the need to develop policy approaches that foster adjustment in the external account while maintaining the growth of output. The purpose of this paper is to develop a macroeconomic model for a small open developing economy that borrows abroad. This model will assist in studying the dynamic interaction between debt and growth, as well as the impact of various policies and exogenous shocks on the rate of capital accumulation, the current account and debt. From this analysis, the authors make the following conclusions. An upward shift in the supply of debt leads to a long run decline in external debt, a higher domestic interest rate, less capital stock, and a reduced trade surplus. An increase in the marginal cost of debt may or may not lower long run external debt as well. An increase in productivity raises the long run stock of capital but leaves the level of external debt and the interest rate unchanged in the long run. Finally, fiscal expansion has almost no effect in either the short run or the long run.Economic Theory&Research,Environmental Economics&Policies,Strategic Debt Management,Banks&Banking Reform,Financial Intermediation

SIMPLE: Stable Increased-throughput Multi-hop Protocol for Link Efficiency in Wireless Body Area Networks

In this work, we propose a reliable, power efficient and high throughput routing protocol for Wireless Body Area Networks (WBANs). We use multi-hop topology to achieve minimum energy consumption and longer network lifetime. We propose a cost function to select parent node or forwarder. Proposed cost function selects a parent node which has high residual energy and minimum distance to sink. Residual energy parameter balances the energy consumption among the sensor nodes while distance parameter ensures successful packet delivery to sink. Simulation results show that our proposed protocol maximize the network stability period and nodes stay alive for longer period. Longer stability period contributes high packet delivery to sink which is major interest for continuous patient monitoring.Comment: IEEE 8th International Conference on Broadband and Wireless Computing, Communication and Applications (BWCCA'13), Compiegne, Franc

Top-Down Integration Methodology for Clocking Blocks into High Speed Serial IO

High Speed Serial Input-Output (HSIOs) design architecture is widely used for many applications in today’s System-On-Chips (SOCs). SOCs integrate a number of protocols including PCIe, SATA, SD4, USB3, etc. which are based on IO architecture. Typical HSIO integrates Analog blocks such as Receiver (Rx), Transmitter (Tx) and Clocking (PLL, Clock Distribution) functions along with sea of logic gates for PCS (Physical Connectivity Sub layer), logic micro-partitions for Tx/Rx power management, encoding/decoding and Serialization/Deserialization functions. The top level design database is typically RTL leading to a sea of gates when synthesized. The top level design is implemented using standard ASIC design flow including RTL, Simulation, Synthesis, Timing, Place & Route, and Formal Verification etc. However, the partitions for Tx, Rx, PLL and Clocking are Analog/Custom hard-macros. To ensure proper functionality, integrity (for low power, timing, Place and route, Mixed Signal/IP level validation) we need to model hard-macros in a digital friendly manner. For functionality verification purpose, we model the macro behavior in Verilog, timing needs to be abstracted in industry standard liberty file format (lib file), for place and route we abstract the physical information in LEF/FRAM format etc. In HIP, while there are methods to build these individually, streamlined methodology for building these with consistency, quality and flow friendly manner is missing. The focus of this project is to formulate a methodology for hard-macro integration into top level HSIO database, and apply this for Secure Digital card (SD4) IO that is being developed in IP Blocks. DOI: 10.17762/ijritcc2321-8169.15066